This application relies for priority upon Korean Patent Application No. 2001-19525, filed on Apr. 12, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor device having a gate all around type transistor and to a method of fabricating the same.
As semiconductor devices become more highly integrated, many methods have been developed in order to reduce the size of an individual device formed on a semiconductor substrate and to maximize device performance. One such method involves using a silicon on insulator (SOI) type substrate, and another method involves forming three-dimensional devices such as vertical transistors.
In the case of using the SOI type substrate, it is possible to perfectly isolate devices and thus prevent neighboring devices in a highly integrated semiconductor device structure from affecting each other. Further, the method of using the SOI type substrate provides higher electric pressure resistivity than device region isolation using a junction method, and can reduce the problem of current being generated at a junction under high radiation environment.
However, as representative methods of forming the three-dimensional device, there are a fully depleted lean-channel transistor (DELTA) structure and a gate all around (GAA) structure. A metal oxide semiconductor field effect transistor (MOSFET) of the DELTA structure is disclosed in the U.S. Pat. No. 4,996,574. In the DELTA structure, an active layer forming a channel is formed to have constant width and to be vertically protruded. A gate electrode is formed to surround the vertically protruded channel part. Thus, the height of the protruded part becomes the channel width, and the width of the protruded part becomes the channel layer thickness. In the formed channel, the both sides of the protruded part can be used to get the effect that the channel width is doubled. Thus, it is possible to prevent channel width decrease in accordance with reduction of a device region and thereby, a narrow channel effect in a conventional transistor.
Also, in the case of reducing the width of the protruded part, channel depletion area formed at the both sides can be overlapped, and thus, there is an effect that channel conductivity increases.
But, in the event that a semiconductor device of DELTA structure is embodied at a bulk type silicon substrate, the substrate is manufactured to protrude a part that forms a channel at the substrate, and substrate oxidation is performed at the state that the protruded part is covered with an oxidation barrier layer. If over-oxidation is performed, a part connecting the protruded part and the substrate body is oxidized by oxygen laterally diffused from another part not protected by an oxidation barrier layer. Thus, the channel is isolated from the semiconductor substrate body. In this process, the channel is separated by over-oxidation to make thickness of channel toward the connecting part low. Thus, there is a problem that single crystal layer is damaged by the pressure of the oxidation process.
In the case of using a SOI type substrate for forming a DELTA structure, a SOI layer is etched to have narrow width and form a channel. Thus, it is possible to solve the problem resulting from the over-oxidation occurring when a bulk type substrate is used. But, in case of using the SOI type substrate, consequently, the channel width is limited by the thickness of the SOI layer. A SOI type substrate of a fully depletion type for a highly integrated semiconductor device has a thickness of the SOI layer to be several hundreds angstroms, and thus, there may be a limitation at using the SOI type substrate.
However, according to a GAA structure, an active region pattern is formed of a SOI layer at a conventional SOI type substrate. And, a gate electrode layer is formed to surround a channel part of an active region pattern covered with a gate insulation layer at a gate electrode. Thus, the GAA structure has a similar effect with the DELTA structure.
But, in case of forming the GAA structure, in order to make the gate electrode surround the active region at the channel part, a buried oxide layer under the active region should be etched using an under-cut phenomenon of isotropic etching. In this process, the isotropic etching removes not only a channel bottom of the active region but also bottoms of source/drain regions. Thus, when a gate electrode layer is formed, a gate electrode is formed at the bottoms of not only the channel but also the source/drain regions. Thus, there is a problem that a parasitic capacitance becomes large since the gate electrode is formed at the bottoms of not only the channel but also the source/drain regions when the gate electrode layer is formed.
Therefore, it is an object of the present invention to provide a semiconductor device having a transistor device and a method of fabricating the same in order to reduce problems of the conventional DELTA and GAA structures, where the transistor device has an effect that widens a channel width by forming a three-dimensional structure.
It is another object of the present invention to provide a semiconductor device having a transistor and a method of fabricating the same, where the transistor can reduce the risk that crystal damage occurs at a channel.
The invention is directed to a semiconductor device having a transistor and a method of fabricating such a device. The transistor is formed on a buried oxide layer of a SOI substrate to a certain direction and divided with three regions, that is, source, channel, and drain regions sequentially. In the source/drain regions, a silicon germanium layer and a silicon layer are stacked and in the channel region, there are an active layer pattern, an insulation layer and a gate electrode. The active layer pattern includes a silicon layer continuing from the source/drain regions, and the insulation layer covers the surface of the active layer pattern at least at the channel region. The gate electrode is formed on the buried oxide layer vertically toward the active layer pattern, surrounding the total channel region of the active pattern.
In the present invention, thickness and composition of an insulation layer formed on the surface of the active layer pattern can be different from those formed on the surfaces of the source/drain regions and the channel region, respectively.
In the present invention, in the active layer pattern on the buried oxide layer, the source/drain regions can be formed by stacking a silicon germanium layer and a silicon layer by one layer, respectively, or by alternatively stacking those layers by multiple layers. In the event that the silicon germanium layer and the silicon layer are alternatively stacked by multiple layers, in the channel region, a conductivity material layer is filled to consist of a gate electrode instead of the silicon germanium layer, and the silicon layer is positioned to continue with the silicon layer of the source/drain regions. An insulation layer functioning of a gate insulation layer interposes between the silicon layer and the conductivity material layer composing of the gate electrode.
In the present invention, the active region can be divided with multiple parts formed to a certain direction at the channel region, differently from that the active region forms one pattern at the source/drain regions.
The object can be achieved by a method of fabricating the semiconductor device according to the present invention. The method includes the following steps. A SOI substrate including a SOI layer, a buried oxide layer, and a bottom substrate layer is prepared, where the SOI layer has at least one unit dual layer formed by overlapping a silicon germanium layer and a silicon layer. The SOI layer is patterned to form the active layer pattern to a certain direction. An etch stop layer is stacked on the active layer pattern. The etch stop layer is patterned and removed at the gate region that crosses the active layer pattern at the channel region. The silicon germanium layer is selectively removed to form a cavity at the channel region of the active layer pattern through the isotropic etch. A gate insulation layer is formed to cover the surface of the exposed active layer pattern in the state that the silicon germanium is selectively removed. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity.
An insulation layer may be formed to cover the surface of the active layer pattern before stacking the etch stop layer. Then the insulation layer at the gate region should be removed before selectively removing the silicon germanium layer.
In the step where the SOI layer is patterned to form the active layer pattern, a middle part relevant to the channel region of the active layer pattern can be patterned to be divided by multiple patterns formed in a line.
In the present invention, the insulation layer and the gate insulation layer are preferably formed by thermal-oxidizing the surface of the active region composed of the silicon layer and the silicon germanium layer.